verilog—分频器设计(2)

else

begin count1<=count1+1'b1;end

if(count2=='d25000)

begin div1khz<=~div1khz;count2<=0;end else

begin count2<=count2+1'b1;end if(count6=='d2500)

begin div10khz<=~div10khz;count6<=0;end else

begin count6<=count6+1'b1;end

end

always @(posedge div1khz)

begin

if(count3=='d500)

begin div1hz<=~div1hz;count3<=0;end else

begin count3<=count3+1'b1;end

if(count4=='d250)

begin div2hz<=~div2hz;count4<=0;end else

begin count4<=count4+1'b1;end

if(count5=='d5)

begin div100hz<=~div100hz;count5<=0;end else

begin count5<=count5+1'b1;end if(count5=='d1000)

begin div05hz<=~div05hz;count7<=0;end else

begin count7<=count7+1'b1;end

end

endmodule