SL74HCT374中文资料(4)

SL74HCT374

AC ELECTRICAL CHARACTERISTICS(VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)

Symbol fmax tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tTLH, tTHL CIN COUT

CPD

Power Dissipation Capacitance (Per Flip-Flop) Used to determine the no-load dynamic power consumption:

PD=CPDVCC2f+ICCVCC

Typical @25°C,VCC=5.0 V

65

pF

Parameter

Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4)

Maximum Propagation Delay, Clock to Q (Figures 1 and 4)

Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5)

Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5)

Maximum Output Transition Time, Any Output (Figures 1 and 4)

Maximum Input Capacitance

Maximum Three-State Output Capacitance (Output in High-Impedance State)

Guaranteed Limit 25 °C to -55°C 30 31 30 30 12 10 15

≤85°C 24 39 38 38 15 10 15

≤125°C 20 47 45 45 18 10 15

Unit MHz ns ns ns ns pF pF

TIMING REQUIREMENTS (VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)

Symbol tSU th tw tr, tf

Parameter

Minimum Setup Time, Data to Clock (Figure 3)

Minimum Hold Time, Clock to Data (Figure 3)

Minimum Pulse Width, Clock (Figure 1)

Maximum Input Rise and Fall Times (Figure 1)

25 °C to -55°C 12 5.0 12 500

Guaranteed Limit

≤85°C 15 5.0 15 500

≤125°C 18 5.0 18 500

Unit ns ns ns ns