FPGA可编程逻辑器件芯片EP1S30F1020C5N中文规格书(2)

Chapter 16:Programmable Power and Temperature-Sensing Diodes in Stratix III Devices

Stratix III External Power Supply Requirements

f For possible values of each power supply, refer to the DC and Switchin

g Characteristics

of Stratix III Devices chapter in volume 2 of the Stratix III Device Handbook.

f For detailed guidelines about how to connect and isolate VCCL and VCC power supply

pins, refer to the Stratix III Device Family Pin Connections Guidelines.

Table16–2.Stratix III Power Supply Requirements

Notes to Table16–2:

(1)You can minimize the number of external power sources by driving the left column and supplies with the same voltage regulator. Note that

separate power planes, decoupling capacitors, and ferrite beads are required for VCCA_PLL and VCCPT when implementing this scheme. (2)V CCPD can be either 2.5 V, 3.0 V, or 3.3 V. For a 3.3-V standard, V CCPD = 3.3 V. For a 3.0-V I/O standard, V CCPD = 3.0V. For 2.5 V and below I/O

standards, V CCPD = 2.5V.

(3)This scheme is for VCCIO = 2.5V.

(4)There is one VREF pin per I/O bank. Use an external power supply or a resistor divider network to supply this voltage.

Stratix III Device Handbook, Volume 1