EDA实验报告(6)

实验报告,EDA

module demux4(y0,y1,y2,y3,din,a); output y0,y1,y2,y3; input din; input [1:0]a; reg y0,y1,y2,y3; always@(din,a) begin y0=0; y1=0; y2=0;

y3=0; case(a[1:0]) 2'b00:y0=din; 2'b01:y1=din; 2'b10:y2=din; 2'b11:y3=din; default:; endcase end Endmodule

数字比较器（8位）

lLIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY comp4_1 IS PORT(A:IN DOWNTO 0); B:IN DOWNTO 0);

STD_LOGIC_VECTOR(3 STD_LOGIC_VECTOR(3

YA,YB,YC: OUT STD_LOGIC); END comp4_1;

ARCHITECTURE behave OF comp4_1 IS BEGIN

PROCESS (A,B) BEGIN

IF (A > B) THEN