DAC8501_芯片手册(4)

DAC 芯片~ 16位超级好用,不容错过

TIMING CHARACTERISTICS(1, 2)

VDD = +2.7V to +5.5V; all specifications –40°C to +105°C, unless otherwise noted.

DAC8501E

PARAMETER

t1(3)

DESCRIPTIONSCLK Cycle Time

VDD = 2.7V to 3.6VVDD = 3.6V to 5.5V

t2

SCLK HIGH Time

VDD = 2.7V to 3.6VVDD = 3.6V to 5.5V

t3

SCLK LOW Time

VDD = 2.7V to 3.6VVDD = 3.6V to 5.5V

t4

SYNC to SCLK RisingEdge Setup Time

VDD = 2.7V to 3.6VVDD = 3.6V to 5.5V

t5

Data Setup Time

VDD = 2.7V to 3.6VVDD = 3.6V to 5.5V

t6

Data Hold Time

VDD = 2.7V to 3.6VVDD = 3.6V to 5.5V

t7

SCLK Falling Edge toVDD = 2.7V to 3.6VVDD = 3.6V to 5.5V

t8

Minimum SYNC HIGH Time

VDD = 2.7V to 3.6VVDD = 3.6V to 5.5V

5033

nsns

00

nsns

4.54.5

nsns

55

nsns

00

nsns

22.513

nsns

1313

nsns

5033

nsns

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES: (1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation timingdiagram, below. (3) Maximum SCLK frequency is 30MHz at VDD = +3.6V to +5.5V and 20MHz at VDD = +2.7V to +3.6V.

SERIAL WRITE OPERATION

4

DAC8501

SBAS212A