3-8译码器的VHDL设计

基于EDA的3-8译码器的VHDL设计(使用软件Quartus2),有仿真波形

3-8译码器的VHDL设计

1.实体框图

2.程序设计

正确的程序

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DECODER38A IS

PORT(A2,A1,A0,S1,S2,S3:IN STD_LOGIC;

Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

END ENTITY DECODER38A;

ARCHITECTURE ONE OF DECODER38A IS

SIGNAL S: STD_LOGIC_VECTOR(5 DOWNTO 0);

BEGIN

S<=A2&A1&A0&S1&S2&S3;

WITH S SELECT

Y<="11111110" WHEN "000100",

"11111101" WHEN "001100",

"11111011" WHEN "010100",

"11110111" WHEN "011100",

"11101111" WHEN "100100",

"11011111" WHEN "101100",

"10111111" WHEN "110100",