L1 Cache and TLB Enhancements to the RAMpage Memory Hierarch(13)

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

contextswitchesonmisses,ofthevariationspresentedhere,isabletohidetheincreasinge ectivelatencyofDRAM.IncreasingthesizeoftheTLB,aspredicted,increasedtherangeofSRAMmainmemorypagesizesoverwhichRAMpageisviable,wideningtherangeofchoicesforadesigner.

5Conclusion

ThispaperhasexaminedenhancementstoRAMpage,whichmeasureitspoten-tialforfurtherimprovement,asopposedtosimilarimprovementstoaconven-tionalhierarchy.Asinpreviouswork,RAMpagehasbeenshowntoscalebetterastheCPU-DRAMspeedgapgrows.Inaddition,ithasbeenshownthatcon-textswitchesonmissescantakeadvantageofamoreaggressivecoreincludingabiggerL1cache,andabiggerTLB.Theremainderofthissectionsummarizesresults,outlinesfutureworkandsumsupoverall ndings.

5.1SummaryofResults

Introducingsigni cantlylargerL1caches–evenifthiscouldbedonewith-outproblemswithmeetingclockcycletargets–haslimitedbene ts.Scalingtheclockspeedupbyafactorof8achievesonlyabout77%ofthisspeedupinacon-ventionalhierarchymeasuredhere.RAMpagewithcontextswitchesonmissesisabletomakee ectiveuseofalargerL1cache,andachievessuperlinearspeedupwithrespecttoaslowerclockspeedandsmallerL1cache.Whilethise ectcanonlybeexpectedinRAMpagewithanunrealisticallylargeL1,thisresultshowsthatincreasinglyaggressiveL1cachesarenotasimportantasolutiontothememorywallproblemas ndingalternativeworkonamisstoDRAM.

ThatresultsforRAMpagewithoutcontextswitchesonmissesareanim-provementbutnotassigni cantasresultswithcontextswitchesonmissessug-geststhatattemptsatimprovingassociativityandreplacementstrategywillnotbesu cienttobridgethegrowingCPU-DRAMspeedgap.

LargerTLBs,asexpected,increasetherangeofusefulRAMpageSRAMmainmemorypagesizes,thoughtheperformancebene tontheworkloadmeasuredwasnotsigni cantversuslargerpagesizesandamoremodest-sizedTLB.

5.2FutureWork

ItwouldbeinterestingtomatchRAMpagewithmodelsforsupportingmorethanoneinstructionstream.SMT,whileaddinghardwarecomplexity,isanestablishedapproach[19],withexistingimplementations[3].Anotherthingtoexploreisalternativeinterconnectarchitectures,somultiplerequestsforDRAMcouldbeoverlapped[24].HyperTransport[2]isacandidate.Amoredetailedsimulationmodellingoperatingsysteme ectsaccuratelywouldbeuseful.SimOS

[26],forexample,couldbeused.Furthervariationstoexploreincludevirtually-addressedL1andhardwareTLBmisshandling.Finally,itwouldbeinterestingtobuildaRAMpagemachine.