L1 Cache and TLB Enhancements to the RAMpage Memory Hierarch(2)

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

SRAMmainmemory,noreferencetoupdatetheTLBneedsgotoDRAM,withthepagetableorganizationusedforRAMpage.Secondly,thereisnomismatchbetweenthesizeofpagemappedbytheTLBandthe“linesize”ofthe“lowest-levelcache”,aswouldbethecasewithaconventionalhierarchy.Consequently,theTLBcanmoreeasilybedesignedtomapaspeci cfractionoftheSRAMmainmemory,thanisthecaseforaconventionalcache.

Theroleofincreasinglyaggressiveon-chipcachesalsoneedstobeevaluated,againsttheviewthatsuchcachesaddressthememorywallproblem.Quadruplingthesizeofacachemayhalvethenumberofmisses[28],butsuchexpansionmaynotalwaysbepractical.Increasingthesizeofcachesinanycasemakesithardertoscaleuptheirspeed[11].

TheapproachinthispaperistocompareRAMpagewithaconventional2-levelcachehierarchyasthesizeoftheTLBscalesup,acrossdi erentSRAMmainmemorypagesizes,aswellasavarietyofL1cachesizes,inseparateexperiments.ThesimulatedL2cacheof4Mbytesrunsatathirdoftheissuerateexcludingmisses.Theintentistoemphasizethatevenaveryfast,largeon-chipcacheresultsinalargefractionofrun-timebeingspentwaitingforDRAM.Evenso,giventhatDRAMreferencesarethedominante ectbeingmeasured,afastcacheshouldnotinvalidatethegeneraltrendsbeingstudied.

TLBmeasurementsshowthatbothmodelsseeareductioninTLBmissratesastheTLBsizeincreases,butRAMpagebecomesmoreviablewithsmallerSRAMmainmemorypagesizes.CachemeasurementsshowthatasL1sizeincreases,thefractionoftimespentwaitingforDRAMincreases(evenifoverallruntimedecreases),whichmakestheoptionintheRAMpagehierarchyoftakingacontextswitchonamissmoreattractive.

Theremainderofthispaperisstructuredasfollows.Section2presentsmoredetailoftheRAMpagehierarchyandrelatedresearch.Section3explainstheexperimentalapproach,whileSection4presentsexperimentalresults.Inconclu-sion,Section5,summarizesthe ndingsandoutlinesfuturework.

2Background

TheRAMpagemodelwasproposed[20]inresponsetothememorywall[30,16].ThekeyideaoftheRAMpagemodelistominimizehardwarecomplexity,whilemovingmoreofthememorymanagementintelligenceintosoftware.ARAMpagemachinethereforelooksverylikeaconventionalmodel,exceptthelowest-levelcacheisreplacedbyaconventionally-addressedphysicalmemory,thoughimplementedinSRAMratherthanDRAM.

Anumberofotherapproachestoaddressingthememorywallhavebeenpro-posed.Thissectionsummarizesthememorywallissue,followedbymoredetailofRAMpage.Afterpresentingotheralternatives,theoptionsarediscussed.

2.1MemoryWall

Thememorywallisthesituationwherethee ectofCPUimprovementsbecomesinsigni cantasthespeedimprovementofDRAMbecomesalimitingfactor.Since