L1 Cache and TLB Enhancements to the RAMpage Memory Hierarch(9)

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

Fraction of time at each level32K64K128KTotal L1 size (KB)256K512K(a)Issuerate1GHz(Std)

Fig.3showsrelativetimeseachvariationoftheslowestandfastestCPUspendwaitingforeachlevelofthevarioushierarchies,asL1sizeincreases.The8GHzissueratefortheconventionalhierarchyspendsover40%oftotalexecu-tiontimewaitingforDRAMforthelargestL1cache–inlinewithmeasurementsofthePentium4,whichspends35%ofitstimewaitingforDRAMrunningSPECint2konaverageat2GHz[28].ThisPentium4con gurationcorrespondsroughlytoa6GHzissuerateinthispaper.ThesimilarityofthetimewaitingforDRAMlendssomecredibilitytoourviewthatourresultsarereasonablyinlinewithrealsystems.